VIDEO GENLOCK PLL

Features • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1 MHz for full output clock range • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions • O

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RENESAS

瑞萨

VIDEO GENLOCK PLL

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IDT

VIDEO GENLOCK PLL

Renesas

瑞萨

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

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IDT

Industrial Mobile Handheld Device

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Quad LVDS Line Receiver with Flow-Through Pinout and ?쏧n-Path??Fail-Safe

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Maxim

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