EP1K10中文资料Configuration Devices for SRAM-Based LUT Devices数据手册Intel规格书

描述 Description

This datasheet describes configuration devices for SRAM-based look-up table (LUT) devices.

特性 Features

Configuration devices for SRAM-based LUT devices offer the following features:
■ Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices
■ Easy-to-use four-pin interface
■ Low current during configuration and near-zero standby mode current
■ Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
■ Available in compact plastic packages
■ 8-pin plastic dual in-line (PDIP) package
■ 20-pin plastic J-lead chip carrier (PLCC) package
■ 32-pin plastic thin quad flat pack (TQFP) package
■ EPC2 device has reprogrammable flash configuration memory
■ 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.
1149.1 JTAG interface
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
■ Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable
■ Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
■ nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration 

简介

EP1K10属于集成电路（IC）的FPGA（现场可编程门阵列）。由制造生产的EP1K10FPGA（现场可编程门阵列）FPGA 是用于执行逻辑运算和信息处理的用户可配置集成电路产品，通常具有非常高级别的集成功能。这些器件通常用于代替通用微处理器，其中已知运算将以极高的速度执行，例如用于接收和处理来自高速数据转换器的信息。它们通常需要外部存储设备来存储用户所需的配置，并在启动时重新加载这些配置。