EP1C12中文资料Cyclone FPGA Family Data Sheet数据手册Intel规格书

描述 Description

Introduction
The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices.

特性 Features

The Cyclone device family offers the following features:
■ 2,910 to 20,060 LEs, see Table 1–1
■ Up to 294,912 RAM bits (36,864 bytes)
■ Supports configuration through low-cost serial configuration device
■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard
■ High-speed (640 Mbps) LVDS I/O support
■ Low-speed (311 Mbps) LVDS I/O support
■ 311-Mbps RSDS I/O support
■ Up to two PLLs per device provide clock multiplication and phase shifting
■ Up to eight global clock lines with six clock resources available per
   logic array block (LAB) row
■ Support for external memory, including DDR SDRAM (133 MHz),
   FCRAM, and single data rate (SDR) SDRAM
■ Support for multiple intellectual property (IP) cores, including
   Altera® MegaCore® functions and Altera Megafunctions Partners
   Program (AMPPSM) megafunctions.

简介

EP1C12属于集成电路（IC）的FPGA（现场可编程门阵列）。由制造生产的EP1C12FPGA（现场可编程门阵列）FPGA 是用于执行逻辑运算和信息处理的用户可配置集成电路产品，通常具有非常高级别的集成功能。这些器件通常用于代替通用微处理器，其中已知运算将以极高的速度执行，例如用于接收和处理来自高速数据转换器的信息。它们通常需要外部存储设备来存储用户所需的配置，并在启动时重新加载这些配置。