Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

文件：1.35316 Mbytes 页数：104 Pages

Altera

阿尔特

Cyclone Series Device Thermal Resistance

Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons

文件：157.18 Kbytes 页数：7 Pages

Altera

阿尔特

1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory. The flash memory is used to store conf

文件：456.96 Kbytes 页数：34 Pages

Altera

阿尔特

Enhanced Configuration (EPC) Devices Datasheet

文件：633.77 Kbytes 页数：36 Pages

Altera

阿尔特

Package Information Datasheet for Mature Altera Devices

文件：2.06334 Mbytes 页数：182 Pages

Altera

阿尔特

This datasheet describes enhanced configuration (EPC) devices

文件：621.91 Kbytes 页数：36 Pages

Altera

阿尔特

Package Information Datasheet for Mature Altera Devices

文件：2.063429 Mbytes 页数：182 Pages

Altera

阿尔特

Cyclone FPGA Family

文件：1.14233 Mbytes 页数：94 Pages

Altera

阿尔特

Cyclone Device Handbook, Volume 1

文件：5.60108 Mbytes 页数：385 Pages

etc2List of Unclassifed Manufacturers

etc未分类制造商etc2未分类制造商

Cyclone FPGA Family Data Sheet

Introduction\nThe Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) i The Cyclone device family offers the following features:\n■ 2,910 to 20,060 LEs, see Table 1–1\n■ Up to 294,912 RAM bits (36,864 bytes)\n■ Supports configuration through low-cost serial configuration device\n■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards\n■ Support for 66- and 33-MHz,;

Intel

英特尔