EM78P156E数据手册Elan中文资料规格书

描述 Description

GENERAL DESCRIPTION
EM78P156E is an 8-bit microprocessor with low-power and high-speed CMOS technology. There is a 1K*13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM) within it. It provides a PROTECTION bit to prevent a user’s code from intruding as well as 7 OPTION bits to match the user’s requirements.
Because of the OTP-ROM, the EM78P156E offers users a convenient way to develop and verify their programs.
Moreover, a user’s developed code can be programmed easily by an EMC writer.FEATURES
• Operating voltage range: 2.2V~5.5V
• Available in temperature range: 0°C~70°C
• Operating frequency range: DC ~ 36MHz
• Low power consumption:
   * less than 1.6 mA at 5V/4MHz
   * typical of 15 µA at 3V/32KHz
   * typical of 1 µA during the sleep mode
• 1Kx13 bits on chip ROM
• One security register to prevent the code in the OTP memory from intruding
• One configuration register to match the user’s requirements
• 48x8 bits on chip registers (SRAM)
• 2 bi-directional I/O ports
• 5 level stacks for subroutine nesting
• 8-bit real time clock/counter (TCC) with selective
   signal sources, trigger edges, and overflow interrupt
• Two clocks per instruction cycle
• Power-down mode (SLEEP mode)
• Three available interruptions
   * TCC overflow interrupt
   * Input-port status changed interrupt (wake up from the sleep mode)
   * External interrupt
• Programmable free running watchdog timer
• 8 pull-high pins
• 7 pull-down pins
• 8 open-drain pins
• Two R-option pins
• Package type: SOP, SOIC and DIP
• 99.9% single instruction cycle commands

特性 Features

• Operating voltage range: 2.2V~5.5V
• Available in temperature range: 0°C~70°C
• Operating frequency range: DC ~ 36MHz
• Low power consumption:
   * less than 1.6 mA at 5V/4MHz
   * typical of 15 µA at 3V/32KHz
   * typical of 1 µA during the sleep mode
• 1Kx13 bits on chip ROM
• One security register to prevent the code in the OTP memory from intruding
• One configuration register to match the user’s requirements
• 48x8 bits on chip registers (SRAM)
• 2 bi-directional I/O ports
• 5 level stacks for subroutine nesting
• 8-bit real time clock/counter (TCC) with selective
   signal sources, trigger edges, and overflow interrupt
• Two clocks per instruction cycle
• Power-down mode (SLEEP mode)
• Three available interruptions
   * TCC overflow interrupt
   * Input-port status changed interrupt (wake up from the sleep mode)
   * External interrupt
• Programmable free running watchdog timer
• 8 pull-high pins
• 7 pull-down pins
• 8 open-drain pins
• Two R-option pins
• Package type: SOP, SOIC and DIP
• 99.9% single instruction cycle commands