1Mega x 16 Synchronous DRAM (SDRAM)

Overview The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized

文件：771.44 Kbytes 页数：74 Pages

ETRON

钰创科技

1Mega x 16 Synchronous DRAM (SDRAM)

The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K x 16 bit DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit bank is organized as 2048 rows by • Fast access time: 4.5/5/5/5.5/6.5/7.5 ns\r\n• Fast clock rate: 200/183/166/143/125/100 MHz\r\n• Self refresh mode: standard and low power\r\n• Fully synchronous operation\r\n• Internal pipelined architecture\r\n• 512K x 16 bit x 2-bank\r\n• Programmable Mode registers\r\n - CAS# Latency: 1, 2, or ;

EtronTech

钰创科技

1Mega x 16 Synchronous DRAM (SDRAM)

Overview The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized

文件：757.98 Kbytes 页数：73 Pages

ETRON

钰创科技

1Mega x 16 Synchronous DRAM (SDRAM)

Overview The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized

文件：757.98 Kbytes 页数：73 Pages

ETRON

钰创科技

1Mega x 16 Synchronous DRAM (SDRAM)

Overview The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized

文件：771.44 Kbytes 页数：74 Pages

ETRON

钰创科技