EDI8L32128C17AI中文资料WEDC数据手册PDF规格书

DESCRIPTION

The EDI8L32128C is a high speed, high performance, four megabit density Static RAM organized as a 128Kx32 bit array.

Four Chip Enables, Write Control, and Output Enable provide the user with a flexible memory solution. The user may independently enable each of the four bytes, and, with minimal additional peripheral logic, the unit may be configured as a 256Kx16 or 512Kx8 array.

FEATURES

128Kx32 bit CMOS Static

Random Access Memory Array

Fast Access Times: 12, 15, 17, 20, and 25ns

Individual Byte Enables

ser Configurable Organization with Minimal Additional Logic

Master Output Enable and Write Control

TTL Compatible Inputs and Outputs

Fully Static, No Clocks

Surface Mount Package

68 Lead PLCC, No. 99 (JEDEC MO-47AE)

Small Footprint, 0.990 Sq. In.

Multiple Ground Pins for Maximum Noise Immunity

Single +5V (±5) Supply Operation