EDI8L24129V中文资料WEDC数据手册PDF规格书

DESCRIPTION

The EDI8L24129VxxBC is a 3.3V, three megabit SRAM constructed with three 128Kx8 die mounted on a multi-layer laminate substrate. With 10 to 15ns access times, x24 width and a 3.3V operating voltage, the EDI8L24129V is ideal for creating a single chip memory solution for the Motorola DSP5630x (Figure 3) or a two chip solution for the Analog Devices SHARCTM DSP (Figure 4).

FEATURES

128Kx24 bit CMOS Static

Random Access Memory Array

■ Fast Access Times: 10, 12, and 15ns

■ Master Output Enable and Write Control

■ TTL Compatible Inputs and Outputs

■ Fully Static, No Clocks

Surface Mount Package

■ 119 Lead BGA (JEDEC MO-163), No. 391

■ Small Footprint, 14mm x 22mm

■ Multiple Ground Pins for Maximum

Noise Immunity

Single +3.3V (±5) Supply Operation

DSP Memory Solution

■ Motorola DSP5630xTM

■ Analog Devices SHARCTM