DSP56F826中文资料飞思卡尔数据手册PDF规格书

56F826 General Description

• Up to 40 MIPS at 80MHz core frequency

• DSP and MCU functionality in a unified, C-efficient architecture

• Hardware DO and REP loops

• MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes

• 31.5K × 16-bit words (64KB) Program Flash

• 512 × 16-bit words (1KB) Program RAM

• 2K × 16-bit words (4KB) Data Flash

• 4K × 16-bit words (8KB) Data RAM

• 2K × 16-bit words (4KB) BootFLASH

• Up to 64K × 16-bit words each of external memory expansion for Program and Data memory

• One Serial Port Interface (SPI)

• One additional SPI or two optional Serial Communication Interfaces (SCI)

• One Synchronous Serial Interface (SSI)

• One General Purpose Quad Timer

• JTAG/OnCE™ for debugging

• 100-pin LQFP Package

• 16 dedicated and 30 shared GPIO

• Time-of-Day (TOD) Timer

56F826 Features

Processing Core

• Efficient 16-bit 56800 family controller engine with dual Harvard architecture

• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Two 36-bit accumulators, including extension bits

• 16-bit bidirectional barrel shifter

• Parallel instruction set with unique processor addressing modes

• Hardware DO and REP loops

• Three internal address buses and one external address bus

• Four internal data buses and one external data bus

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C Compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/OnCE Debug Programming Interface