DSP56F805E中文资料飞思卡尔数据手册PDF规格书

General Description

• Up to 40 MIPS at 80MHz core frequency

• DSP and MCU functionality in a unified, C-efficient architecture

• Hardware DO and REP loops

• MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation

unit, 14 addressing modes

• 31.5K ×16-bit words (64KB) Program Flash

• 512 ×16-bit words (1KB) Program RAM

• 4K ×16-bit words (8KB) Data Flash

• 2K ×16-bit words (4KB) Data RAM

• 2K ×16-bit words (4KB) Boot Flash

• Up to 64K ×16-bit words (128KB) each of external Program and Data memory

• Two 6-channel PWM Modules

• Two 4-channel, 12-bit ADCs

• Two Quadrature Decoders

• CAN 2.0 B Module

• Two Serial Communication Interfaces (SCIs)

• Serial Peripheral Interface (SPI)

• Up to four General Purpose Quad Timers

• JTAG/OnCETM port for debugging

• 14 Dedicated and 18 Shared GPIO lines

• 144-pin LQFP Package

• Up to 40 MIPS at 80MHz core frequency

• DSP and MCU functionality in a unified,

C-efficient architecture

• Hardware DO and REP loops

• MCU-friendly instruction set supports both DSP

and controller functions: MAC, bit manipulation

unit, 14 addressing modes

• 31.5K ×16-bit words (64KB) Program Flash

• 512 ×16-bit words (1KB) Program RAM

•4K ×16-bit words (8KB) Data Flash

•2K ×16-bit words (4KB) Data RAM

•2K ×16-bit words (4KB) Boot Flash

• Up to 64K ×16-bit words (128KB) each of external

Program and Data memory

• Two 6-channel PWM Modules

• Two 4-channel, 12-bit ADCs

• Two Quadrature Decoders

• CAN 2.0 B Module

• Two Serial Communication Interfaces (SCIs)

• Serial Peripheral Interface (SPI)

• Up to four General Purpose Quad Timers

• JTAG/OnCE

TM

port for debugging

• 14 Dedicated and 18 Shared GPIO lines

• 144-pin LQFP Package

General Description