DSP56307中文资料恩智浦数据手册PDF规格书

FEATURES

High-Performance DSP56300 Core

¥ 100 million instructions per second (MIPS) with a 100 MHz clock at 2.5 V core and

3.3 V I/O

¥ Object code compatible with the DSP56000 core

¥ Highly parallel instruction set

¥ Data arithmetic logic unit (ALU)

Ð Fully pipelined 24 x 24-bit parallel multiplier-accumulator

Ð 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and

parsing)

Ð Conditional ALU instructions

Ð 24-bit or 16-bit arithmetic support under software control

¥ Program control unit (PCU)

Ð Position independent code (PIC) support

Ð Addressing modes optimized for DSP applications (including immediate offsets)

Ð On-chip instruction cache controller

Ð On-chip memory-expandable hardware stack

Ð Nested hardware DO loops

Ð Fast auto-return interrupts

¥ Direct memory access (DMA)

Ð Six DMA channels supporting internal and external accesses

Ð One-, two-, and three- dimensional transfers (including circular buffering)

Ð End-of-block-transfer interrupts

Ð Triggering from interrupt lines and all peripherals

¥ Phase-locked loop (PLL)

Ð Allows change of low power divide factor (DF) without loss of lock

Ð Output clock with skew elimination

¥ Hardware debugging support

Ð On-Chip Emulation (OnCE

Ô

) module

Ð Joint test action group (JTAG) test access port (TAP)

Ð Address trace mode reflects internal Program RAM accesses at the external port

APPLICATIONS

The DSP56307 is intended for applications requiring a large amount of on-chip memory, such as

wireless infrastructure applications. The EFCOP may be used to accelerate general filtering

applications, such as echo-cancellation applications, correlation, and general purpose

convolution-based algorithms.