DSP56303PV100中文资料恩智浦数据手册PDF规格书

Features

High-Performance DSP56300 Core

• 100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal

• Object code compatible with the DSP56000 core with highly parallel instruction set

• Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel multiplier-accumulator (MAC),

56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional

ALU instructions, and 24-bit or 16-bit arithmetic support under software control

• Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for

DSP applications (including immediate offsets), internal instruction cache controller, internal memoryexpandable

hardware stack, nested hardware DO loops, and fast auto-return interrupts

• Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-

, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and

triggering from interrupt lines and all peripherals

• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock

with skew elimination

• Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG)

test access port (TAP)

Applications

Examples include:

• Multi-line voice/data/fax processing

• Video conferencing

• Audio applications

• Control