DSP56002PV66中文资料恩XP数据手册PDF规格书

FEATURES

• Efficient 24-bit DSP56000 core

• Up to 40 Million Instructions Per Second (MIPS), 25 ns instruction cycle at

80 MHz; up to 33 MIPS, 30.3 ns instruction cycle at 66 MHz

• Up to 240 Million Operations Per Second (MOPS) at 80 MHz; up to 198 MOPS

at 66 MHz

• Performs a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks

• Highly parallel instruction set with unique DSP addressing modes

• Two 56-bit accumulators including extension bits

• Parallel 24

´

24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)

• Double precision 48

´

48-bit multiply with 96-bit result in 6 instruction cycles

• 56-bit addition/subtraction in 1 instruction cycle

• Fractional and integer arithmetic with support for multiprecision arithmetic

• Hardware support for block-floating point FFT

• Hardware nested DO loops

• Zero-overhead fast interrupts (2 instruction cycles)

• Four 24-bit internal data buses and three 16-bit internal address buses for

maximum information transfer on-chip