DS92LV3242中文资料20-85MHz 32 位频道链接 II 解串器数据手册TI规格书

描述 Description

The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or 4 (selectable) embedded clock LVDS serial channels for a data payload rate up to 2.72 Gbps over cables such as CATx, or backplanes FR-4 traces. The companion DS92LV3242 (DES) deserializes the 2 or 4 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus.On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Pre-emphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing an easy “plug-and-lock” operation. By embedding the clock in the data payload and including signal conditioning functions, the Channel-Link II SerDes devices reduce trace count, eliminate skew issues, simplify design effort and lower cable/connector cost for a wide variety of video, control and imaging applications. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.

特性 Features

• Wide Operating Range Embedded Clock SER/DES
• 20 to 85 MHz Parallel Clock
• Selectable Serial LVDS Bus Width
• Quad Lane Mode (40 to 85 MHz)
• Simplified Clocking Architecture
• No reference Clock Required
• On-Chip Signal Conditioning for Robust Serial Connectivity
• Data Randomization
• Receive Channel Deskew
• Integrated LVDS Terminations
• AC-Coupled Interconnect for Isolation and Fault Protection
• Space-Saving 64-pin TQFP Package
• Full Industrial Temperature Range : -40° to +85°C