DS92LV1023MWC数据手册TI中文资料规格书

描述 Description

General Description
The DS92LV1023 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1224 receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock. The DS92LV1023 transmits data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits clock and data bits serially, it eliminates clock-to-data and data-to-data skew.

特性 Features

Clock recovery from PLL lock to random data patterns.
Guaranteed transition every data transfer cycle
Chipset (Tx + Rx) power consumption < 500 mW (typ) @ 66 MHz
Single differential pair eliminates multi-channel skew
Flow-through pinout for easy PCB layout
660 Mbps serial Bus LVDS data rate (at 66 MHz clock)
10-bit parallel interface for 1 byte data plus 2 control bits
Synchronization mode and LOCK indicator
Programmable edge trigger on clock
High impedance on receiver inputs when power is off
Bus LVDS serial output rated for 27Ω load
Small 28-lead SSOP package