DS92LV0421中文资料具有 LVDS 并行接口的 10MHz 至 75MHz Channel-Link II 串行器数据手册TI规格书

描述 Description

The DS92LV042x chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized interface over a single CML pair. The DS92LV042x enables applications currently using popular Channel Link or OpenLDI LVDS style devices to upgrade seamlessly to an embedded clock interface. This serial bus scheme reduces interconnect cost and eases design challenges. The parallel OpenLDI LVDS interface also reduces FPGA I/O pins, board trace count, and alleviates EMI issues when compared to traditional single-ended wide bus interfaces.

Programmable transmit de-emphasis, receive equalization, on-chip scrambling, and DC-balancing enables longer distance transmission over lossy cables and backplanes. The DS92LV0422 automatically locks to incoming data without an external reference clock or special sync patterns, providing easy operation.

The DS92LV042x chipset is programmable through an I2C interface as well as through pins. A built-in, at-speed BIST feature validates link integrity and may be used for system diagnostics. The DS92LV0421 and DS92LV0422 can be used interchangeably with the DS92LV2421 or DS92LV2422. This allows designers the flexibility to connect to the host device and receiving devices with different interface types: LVDS or LVCMOS.

特性 Features

• 5-Channel (4 Data + 1 Clock) Channel Link LVDS Parallel Interface Supports 24-Bit Data 3-Bit Control at 10 to 75 MHz
• AC-Coupled STP Interconnect Up to 10 m
• Integrated Terminations on Serializer and Deserializer
• At-Speed Link BIST Mode and Reporting Pin
• Optional I2C-Compatible Serial Control Bus
• Power-Down Mode Minimizes Power Dissipation
• 1.8-V or 3.3-V Compatible LVCMOS I/O Interface
• >8-kV HBM
• –40° to 85°C Temperature Range
• Serializer (DS92LV0421)
• Data Scrambler for Reduced EMI
• DC-Balance Encoder for AC Coupling
• Selectable Output VOD and Adjustable De-Emphasis

• Deserializer (DS92LV0422)
• Fast Random Data Lock; No Reference Clock Required
• Adjustable Input Receiver Equalization
• EMI Minimization on Output Parallel Bus (SSCG and LVDS VOD Select)