丝印：DS90CR482VS；Package：TQFP；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

文件：1.21572 Mbytes 页数：26 Pages

TI

德州仪器

丝印：DS90CR482VS；Package：TQFP；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

文件：1.21572 Mbytes 页数：26 Pages

TI

德州仪器

丝印：DS90CR482VS；Package：TQFP；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

文件：1.21572 Mbytes 页数：26 Pages

TI

德州仪器

丝印：DS90CR482VS；Package：TQFP；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

文件：1.21572 Mbytes 页数：26 Pages

TI

德州仪器

丝印：DS90CR482VS；Package：TQFP；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

文件：1.21572 Mbytes 页数：26 Pages

TI

德州仪器

丝印：DS90CR482VS；Package：TQFP；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

文件：1.21572 Mbytes 页数：26 Pages

TI

德州仪器

丝印：DS90CR482VS；Package：TQFP；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

文件：1.21572 Mbytes 页数：26 Pages

TI

德州仪器

丝印：DS90CR482VS；Package：TQFP；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

文件：1.21572 Mbytes 页数：26 Pages

TI

德州仪器

丝印：DS90CR482VS；Package：TQFP；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

文件：1.21572 Mbytes 页数：26 Pages

TI

德州仪器

丝印：DS90CR482VS；Package：TQFP；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

文件：1.21572 Mbytes 页数：26 Pages

TI

德州仪器