丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器