DS90CR283数据手册集成电路（IC）的专用规格书PDF

描述 Description

General Description
The DS90CR283 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR284 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 28 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.848 Gbit/s (231 Mbytes/s).

特性 Features

  66 MHz clock support
  Up to 231 Mbytes/s bandwidth
  Low power CMOS design (< 610 mW)
  Power Down mode (< 0.5 mW total)
  Up to 1.848 Gbit/s data throughput
  Narrow bus reduces cable size and cost
  290 mV swing LVDS devices for low EMI
  PLL requires no external components
  Low profile 56-lead TSSOP package
  Rising edge data strobe
  Compatible with TIA/EIA-644 LVDS Standard