DS90CF363AMTD数据手册TI中文资料规格书

描述 Description

+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz
+3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHzGeneral Description
The DS90C363A/DS90CF363A transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential
Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel.

特性 Features

20 to 65 MHz shift clock support
Rejects±3ns Jitter from VGA chip with less than 225ps output Jitter@65MHz (TJCC)
Best–in–Class Set & Hold Times on TxINPUTs
Tx power consumption<130 mW (typ)@65MHz Grayscale
50%Less Power Dissipation than BiCMOS Alternatives
Tx Power-down mode<200µW (max)
ESD rating7 kV (HBM),500V (EIAJ)
Supports VGA, SVGA, XGA and Dual Pixel SXGA.
Narrow bus reduces cable size and cost
Up to 1.3 Gbps throughput
Up to 170 Megabytes/sec bandwidth
345 mV (typ) swing LVDS devices for low EMI
PLL requires no external components
Compatible with TIA/EIA-644 LVDS standard
Low profile 48-lead TSSOP package
Improved replacement for:
  SN75LVDS85 — DS90C363A
  SN75LVDS84 — DS90CF363A