3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

文件：258.44 Kbytes 页数：11 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz 3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

文件：304.25 Kbytes 页数：11 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz 3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

文件：304.25 Kbytes 页数：11 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz 3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

文件：304.25 Kbytes 页数：11 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

文件：258.44 Kbytes 页数：11 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

General Description\nThe DS90C383A/DS90CF383A transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bi ■ 20 to 65 MHz shift clock support\n■ Rejects ± 3ns Jitter from VGA chip with less than 225ps output Jitter @65MHz (TJCC)\n■ Best–in–Class Set & Hold Times on TxINPUTs\n■ Tx power consumption <130 mW (typ) @65MHz Grayscale\n■ 50% Less Power Dissipation than BiCMOS Alternatives\n■ Tx Power-down ;

TI

德州仪器