DS90C365AMTXSLASHNOPB.A中文资料德州仪器数据手册PDF规格书

PDF无图
厂商型号

DS90C365AMTXSLASHNOPB.A

功能描述

3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz

丝印标识

DS90C365AMT

封装外壳

TSSOP

文件大小

663.87 Kbytes

页面数量

20

生产厂商

TI

中文名称

德州仪器

网址

网址

数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-10-5 16:11:00

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DS90C365AMTXSLASHNOPB.A价格和库存,欢迎联系客服免费人工找货

DS90C365AMTXSLASHNOPB.A规格书详情

1FEATURES

23• Pin-to-pin compatible to DS90C363,

DS90C363A and DS90C365

• No special start-up sequence required

between clock/data and /PD pins. Input signals

(clock and data) can be applied either before

or after the device is powered.

• Support Spread Spectrum Clocking up to

100kHz frequency modulation & deviations of

±2.5% center spread or -5% down spread.

• “Input Clock Detection” feature will pull all

LVDS pairs to logic low when input clock is

missing and when /PD pin is logic high.

• 18 to 87.5 MHz shift clock support

• Tx power consumption < 146 mW (typ) at 87.5

MHz Grayscale

• Tx Power-down mode < 37 uW (typ)

• Supports VGA, SVGA, XGA, SXGA (dual pixel),

SXGA+ (dual pixel), UXGA (dual pixel).

• Narrow bus reduces cable size and cost

• Up to 1.785 Gbps throughput

• Up to 223.125 Megabytes/sec bandwidth

• 345 mV (typ) swing LVDS devices for low EMI

• PLL requires no external components

• Compliant to TIA/EIA-644 LVDS standard

• Low profile 48-lead TSSOP package

DESCRIPTION

The DS90C365A is a pin to pin compatible

replacement for DS90C363, DS90C363A and

DS90C365. The DS90C365A has additional features

and improvements making it an ideal replacement for

DS90C363, DS90C363A and DS90C365. family of

LVDS Transmitters.

The DS90C365A transmitter converts 21 bits of

LVCMOS/LVTTL data into four LVDS (Low Voltage

Differential Signaling) data streams. A phase-locked

transmit clock is transmitted in parallel with the data

streams over the fourth LVDS link. Every cycle of the

transmit clock 21 bits RGB of input data are sampled

and transmitted. At a transmit clock frequency of 87.5

MHz, 21 bits of RGB data and 3 bits of LCD timing

and control data (FPLINE, FPFRAME, DRDY) are

transmitted at a rate of 612.5 Mbps per LVDS data

channel. Using a 87.5 MHz clock, the data throughput

is 229.687 Mbytes/sec. This transmitter can be

programmed for Rising edge strobe or Falling edge

strobe through a dedicated pin. A Rising edge or

Falling edge strobe transmitter will interoperate with a

Falling edge strobe FPDLink Receiver without any

translation logic.

This chipset is an ideal means to solve EMI and

cable size problems associated with wide, high-speed TTL interfaces with added Spead Spectrum Clocking

support..

供应商 型号 品牌 批号 封装 库存 备注 价格
NS/国半
2402+
TSSOP-48
8324
原装正品!实单价优!
询价
NS/国半
23+
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32732
原装正品代理渠道价格优势
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原厂正品
23+
LQFP64
5000
原装正品,假一罚十
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NS
24+
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9600
原装现货,优势供应,支持实单!
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NS/国半
2447
SSOP
100500
一级代理专营品牌!原装正品,优势现货,长期排单到货
询价
NS
24+
TSSOP
64
询价
TI/德州仪器
23+
TSSOP
8215
原厂原装
询价
NS
23+
TSSOP
65480
询价
NS
20+
TSSOP
2960
诚信交易大量库存现货
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NS
24+
TSSOP
5645
公司原厂原装现货假一罚十!特价出售!强势库存!
询价