DS7837数据手册TI中文资料规格书

描述 Description

General Description
The DS7837/DS8837 are high speed receivers designed for use in bus organized data transmission systems interconnected by terminated 120Ximpedance lines. The external termination is intended to be 180Xresistor from the bus to the a5V logic supply together with a 390Xresistor from the bus to ground. The receiver design employs a built-in input hysteresis providing substantial noise immunity. Low input current allows up to 27 driver/receiver pairs to utilize a common bus. Disable inputs provide time discrimination. Disable inputs and receiver outputs are TTL compatible. Perform
ance is optimized for systems with bus rise and fall times s1.0ms/V.

特性 Features

Low receiver input current for normal VCC or VCC= 0V (15 mA typ)
Six separate receivers per package
Built-in receiver input hysteresis (1V typ)
High receiver noise immunity (2V typ)
Temperature insensitive receiver input thresholds track bus logic levels
TTL compatible disable and output
Molded or cavity dual-in-line or flat package
High speed