DS7836数据手册TI中文资料规格书

描述 Description

General Description
The DS7836/DS8836 are quad 2-input receivers designed for use in bus organized data transmission systems interconnected by terminated 120Ximpedance lines. The external termination is intended to be 180Xresistor from the bus to the a5V logic supply together with a 390Xresistor from the bus to ground. The design employs a built-in input hysteresis providing substantial noise immunity. Low input current allows up to 27 driver/receiver pairs to utilize a common bus. Performance is optimized for systems with bus rise and fall times s1.0ms/V.

特性 Features

Low input current with normal VCC or VCC = 0V (15 mA typ)
Built-in input hysteresis (1V typ)
High noise immunity (2V typ)
Temperature-insensitive input thresholds track bus logic levels
TTL compatible output
Matched, optimized noise immunity for ``1'' and ``0'' levels
High speed (18 ns typ)