DS31406数据手册集成电路（IC）的应用特定时钟/定时规格书PDF

描述 Description

The DS31406 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its two input clocks and 14 output clocks, the device can accept or generate nearly any frequency between 2kHz and 750MHz.

The input clocks are divided down, fractionally scaled as needed, and continuously monitored for activity and frequency accuracy. The best input clock is selected, manually or automatically, as the reference clock for the rest of the device. A flexible, high-performance digital PLL locks to the selected reference and provides programmable bandwidth, very high resolution holdover capability and truly hitless switching between input clocks. The digital PLL is followed by a clock synthesis subsystem that has seven fully programmable digital frequency synthesis blocks, three high-speed low-jitter APLLs, and 14 output clocks, each with its own 32-bit divider and phase adjustment. The APLLs provide fractional scaling and output jitter less than 1ps RMS.

For telecom systems, the DS31406 has all required features and functions to serve as a central timing function or as a line card timing IC. With a suitable oscillator the DS31406 meets the requirements of Stratum 2, 3E, 3, 4E, and 4, G.812 Types I–IV, G.813, and G.8262.

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特性 Features

Two Input Clocks
• Differential or CMOS/TTL Format
• Any Frequency from 2kHz to 750MHz
• Fractional Scaling for 64B/66B and FEC Scaling (e.g. 64/66, 237/255, 238/255) or Any Other Downscaling Requirement
• Continuous Input Clock Quality Monitoring
• Automatic or Manual Clock Selection
• Two 2/4/8kHz Frame Sync Inputs
High-Performance DPLL
• Hitless Reference Switching on Loss of Input
• Automatic or Manual Phase Build-Out
• Holdover on Loss of All Inputs
• Programmable Bandwidth, 0.5mHz to 400Hz
Seven Digital Frequency Synthesizers
• Produce Any 2kHz Multiple Up to 77.76MHz
• Per-DFS Clock Phase Adjust
Three Output APLLs
• Output Frequencies to 750MHz
• High Resolution Fractional Scaling for FEC and 64B/66B (e.g., 255/237, 255/238, 66/64) or Any Other Scaling Requirement
• Less than 1ps RMS Output Jitter
• Simultaneously Produce Three Low-Jitter Rates from the Same Reference (e.g., 622.08MHz for SONET, 255/237*622.08MHz for OTU2, and 156.25MHz for 10GE)
14 Output Clocks in Seven Groups
• Nearly Any Frequency from General Features
• Suitable Line Card IC or Timing Card IC for Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU
• Accepts and Produces Nearly Any Frequency Up to 750MHz Including 1Hz, 2kHz, 8kHz, NxDS1, NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M, 156.25M, and Nx19.44M Up to 622.08M
• Internal Compensation for Local Oscillator Frequency Error
• SPI™ Processor Interface
• 1.8V Operation with 3.3V I/O (5V Tolerant)
Applications/Uses
• IEEE 1588 Time/Frequency Clocks
• MSPPs
• Routers
• SONET/SDH
• Switches
• Synchronous Ethernet

简介

DS31406属于集成电路（IC）的应用特定时钟/定时。由制造生产的DS31406应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。