DS31404数据手册集成电路（IC）的应用特定时钟/定时规格书PDF

描述 Description

The DS31400 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its eight input clocks and 14 output clocks, the device can accept or generate any frequency between 2kHz and 750MHz. The device offers two independent DPLLs to serve two independent clock-generation paths.

The input clocks are divided down, fractionally scaled as needed, and continuously monitored for activity and frequency accuracy. The best input clock is selected, manually or automatically, as the reference clock for each of the two digital PLLs. Each DPLL locks to the selected reference and provides programmable bandwidth, very high-resolution holdover capability and truly hitless switching between input clocks. The digital PLLs are followed by a clock synthesis subsystem that has seven fully programmable digital frequency synthesis blocks, three high-speed low-jitter APLLs, and 14 output clocks, each with its own 32-bit divider and phase adjustment. The APLLs provide fractional scaling and output jitter less than 1ps RMS.

For telecom systems, the device has all required features and functions to serve as a central timing function or as a line card timing IC. With a suitable oscillator, the device meets the requirements of Stratum 2, 3E, 3, 4E, and 4; G.812 Types I to IV; G.813; and G.8262. The device has full support for Synchronous Ethernet clock frequencies.

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特性 Features

Four Input Clocks
• Differential or CMOS/TTL Format
• Any Frequency from 2kHz to 750MHz
• Fractional Scaling for 64B/66B and FEC Scaling (e.g., 64/66, 237/255, 238/255) or Any Other Downscaling Requirement
• Continuous Input Clock Quality Monitoring
• Automatic or Manual Clock Selection
• Three 2/4/8kHz Frame Sync Inputs
Two High-Performance DPLLs
• Hitless Reference Switching on Loss of Input
• Automatic or Manual Phase Build-Out
• Holdover on Loss of All Inputs
• Programmable Bandwidth, 0.5mHz to 400Hz
Four Digital Frequency Synthesizers
• Each Can Slave to Either DPLL
• Produce Any 2kHz Multiple Up to 77.76MHz
• Per-DFS Clock Phase Adjust
Two Output APLLs
• Output Frequencies to 750MHz
• High-Resolution Fractional Scaling for FEC and 64B/66B (e.g., 255/237, 255/238, 66/64) or Any Other Scaling Requirement
• Less Than 1ps RMS Output Jitter
• Simultaneously Produce Two Low-Jitter Rates from the Same Reference (e.g., 622.08MHz for SONET and 156.25MHz for 10GE)
Eight Output Clocks in Four Groups
• Nearly Any Frequency from General Features
• Suitable Line Card IC or Timing Card IC for Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU
• Accepts and Produces Nearly Any Frequency Up to 750MHz Including 1Hz, 2kHz, 8kHz, NxDS1, NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M, 156.25M, and Nx19.44M Up to 622.08M
• Internal Compensation for Local Oscillator Frequency Error
• SPI™ Processor Interface
• 1.8V Operation with 3.3V I/O (5V Tolerant)
Applications/Uses
• MSPPs
• Routers
• SONET/SDH
• Switches
• Synchronous Ethernet

简介

DS31404属于集成电路（IC）的应用特定时钟/定时。由制造生产的DS31404应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。