DS1007中文资料7合1硅延迟线数据手册ADI规格书

描述 Description

The DS1007 7-in-1 Silicon Delay Line reproduces an input logic state at the output after delays at 7 taps. Delays from range from 3ns to 40ns (see table), with a tolerance of ±2ns at room temperature.
By enabling precise timing adjustments, Dallas Silicon Delay Lines improve system performance. They provide an effective, economical solution to the designer working with the complex timing requirements of mismatched ASICs or other components, or with the strict timing tolerances of increasing system clock rates. Each delay line die is laser-optimized and molded into a space-saving SOIC package.

特性 Features

• All-silicon timed delay circuit
• 7 independent, buffered delays
• Delay tolerance ±2ns
• Custom settings:
• Four delays can be set between 3ns and 10ns
• Three delays can be set between 9ns and 40ns
• Low-power CMOS with TTL compatibility
• Vapor phase, IR, and wave-solderable

简介

DS1007属于集成电路（IC）的延迟线。由制造生产的DS1007延迟线时钟延迟线产品族中的产品属于数字器件，用于在数字信号中引入时间延迟，以便将提交给器件输入的信号跃迁，经过某一已知时间之后在输出端复现。它们常用于高速数字系统，以校正或补偿不同信号路径之间的信号传播时间的偏差。这些器件可用于产生固定、可选或可变持续时间的延迟。