DS1004中文资料5抽头、高速硅延迟线数据手册ADI规格书

描述 Description

The DS1004 5-Tap High-Speed Silicon Delay Line reproduces an input logic state at the output after a minimum input-to-tap delay of 5ns at Tap 1, with Taps 2 to 5 precisely delayed by 2, 3, 4, or 5ns. Nominal delay tolerances are characterized at standard conditions of +25°C and +5V, with added tolerances over nonstandard temperature and voltage. Leading and trailing edges are reproduced with equal precision. Each tap output is capable of driving up to ten 74LS loads.
By enabling precise timing adjustments, Dallas Silicon Delay Lines improve system performance. They provide an effective, economical solution to the designer working with the complex timing requirements of mismatched ASICs or other components, or with the strict timing tolerances of increasing system clock rates. Each delay line die is laser-optimized and molded into a space-saving SOIC package.

特性 Features

• All-silicon timing delay circuit
• 5 delayed clock phases per input
• Input to Tap 1 delay set at 5ns
• Taps 2-5 delay range: 2, 3, 4, or 5ns
• Nominal delay tolerances of ±1.5ns
• Same accuracy for leading and trailing edges
• Low-power CMOS with TTL compatibility
• Vapor phase, IR, and wave solderable

简介

DS1004属于集成电路（IC）的延迟线。由制造生产的DS1004延迟线时钟延迟线产品族中的产品属于数字器件，用于在数字信号中引入时间延迟，以便将提交给器件输入的信号跃迁，经过某一已知时间之后在输出端复现。它们常用于高速数字系统，以校正或补偿不同信号路径之间的信号传播时间的偏差。这些器件可用于产生固定、可选或可变持续时间的延迟。