DP83TC814X-Q1中文资料德州仪器数据手册PDF规格书

1 Features

• IEEE 802.1AE MACsec

– MACsec frame expansion: Inbuilt buffering and

flow control support to handle 12 byte IPG

Ethernet frames

– Authentication, encryption at line rate

– Cipher suites: GCM-AES-XPN-128/256, GCMAES-

128/256

– Secure Channel: Total 16 SAK enabling 8

Tx/Rx SC

– Auto rollover support for SAK

– Ingress/Egress classification for Ethertype,

VLAN, DMAC: up to 8 parallel rules

– Window replay protection

• IEEE 802.1AS time synchronization

– Highly accurate 1pps signal

• Synchronization Jitter: < ±15ns (options to

reduce to ±1ns)

• Synchronization Offset: < ±30ns

– Precise time stamping for MACsec encoded

PTP packets

– Multiple IOs for event capture and trigger

• IEEE 802.3bw, OA 100BASE-T1 and TC-10

compliant

– < 18μA sleep current

– Fast wake from sleep by retaining PHY

configuration during sleep (optional)

• Robust EMC Performance

– IEC62228-5, OA EMC compliant

– SAE J2962-3 EMC compliant

– 39dBm DPI Immunity with ±5% assymetry

– <4dBμV radiated emissions in GPS and

Glonass bands

– Stripline Emissions: Class-II compliant

• MAC Interfaces: MII, RMII, RGMII, SGMII

• Footprint compatible with TI's 1000BASE-T1 PHY

– Single board design for 100BASE-T1 and

1000BASE-T1 with required BOM change

• Diagnostic tool kit

– Signal Quality Indication (SQI) & Time Domain

Reflectometry (TDR)

– Voltage, Temperature & ESD sensors

– PPM monitor: Provides external clock ppm drift

(up to ±100ppb accuracy)

• AEC-Q100 qualified for Automotive Applications:

– Temperature Grade 1: –40°C to +125 °C

– IEC61000-4-2 ESD level 4 MDI: ±8kV CD

2 Applications

• ADAS

– Radar Synchronization

• Body Electronics & Lighting

– Body Control Module

– Zone Control Module

• Telematics

3 Description

The DP83TC817S-Q1 is an IEEE 802.3bw and

Open Alliance (OA) compliant automotive qualified

100Base-T1 Ethernet physical layer transceiver. The

device provides all physical layer functions needed

to transmit and receive data over unshielded/shielded

single twisted-pair cables with xMII interface flexibility.

The DP83TC817S-Q1 integrates IEEE 802.1AE

line rate security with authentication and optional

encryption support to secure communication over

the network. The PHY supports up to 16 secure

association (SA) channels with automatic SAK

rollover and extended packet numbering support.

DP83TC817S-Q1 offers ingress classification to filter

the unwanted packets & supports WAN MACsec for

end-to-end security.

The DP83TC817S-Q1 integrates IEEE802.1AS /

IEEE1588v2 to enable highly accurate time

synchronization and hardware time stamping for

time-sensitive, real-time controlled applications, with

support for encrypted PTP packets.

The DP83TC817S-Q1 supports OA TC-10 low power

sleep feature with wake forwarding for reduced

system power consumption when communication is

not required.

The DP83TC817S-Q1 is footprint compatible to

TI's 100BASE-T1 PHYs and 1000BASE-T1 PHYs

enabling design scalability with a single board for

different speeds and features.