DMA90401数据手册贸易商松下PANASONIC-114ic电子网

首页 >DMA90401>规格书列表

型号	下载订购	功能描述	制造商上传企业	LOGO
DMA90401	文件：389.86 Kbytes Page：4 Pages	Silicon PNP epitaxial planar type For general amplification DMA50401 in SSMini6 type package 文件：389.86 Kbytes 页数：4 Pages	PANASONIC 松下	PANASONIC
DMA90401	文件：300 bytes Page：1 Pages	Silicon PNP epitaxial planar type For general amplification DMA50401 in SSMini6 type package	Panasonic 松下	Panasonic
MT90401	文件：650.4 Kbytes Page：38 Pages	SONET/SDH System Synchronizer Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by 文件：650.4 Kbytes 页数：38 Pages	ZARLINK Zarlink Semiconductor Inc	ZARLINK
MT90401	文件：249.12 Kbytes Page：21 Pages	SONET/SDH Clock Multiplier PLL 文件：249.12 Kbytes 页数：21 Pages	ZARLINK Zarlink Semiconductor Inc	ZARLINK
MT90401AB	文件：650.4 Kbytes Page：38 Pages	SONET/SDH System Synchronizer Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by 文件：650.4 Kbytes 页数：38 Pages	ZARLINK Zarlink Semiconductor Inc	ZARLINK

更多DMA90401供应商更新时间2026-4-12 14:00:00