Triple 3-Input AND Gate

General Description This device contains three independent gates each of which performs the logic AND function.

文件：33.6 Kbytes 页数：3 Pages

Fairchild

仙童半导体

Triple 3-Input AND Gate

ONSEMI

安森美半导体

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

文件：43.5 Kbytes 页数：4 Pages

Fairchild

仙童半导体

Triple 3-Input AND Gate

General Description This device contains three independent gates each of which performs the logic AND function.

文件：33.6 Kbytes 页数：3 Pages

Fairchild

仙童半导体

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

ONSEMI

安森美半导体

Package：16-DIP（0.300"，7.62mm）；包装：袋 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 16DIP

ONSEMI

安森美半导体

Package：14-DIP（0.300"，7.62mm）；包装：袋 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 14DIP

ONSEMI

安森美半导体

Package：14-DIP（0.300"，7.62mm）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 门和反相器 描述：IC GATE AND 3CH 3-INP 14DIP

ONSEMI

安森美半导体