Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

文件：43.5 Kbytes 页数：4 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

ONSEMI

安森美半导体

Package：16-DIP（0.300"，7.62mm）；包装：袋 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 16DIP

ONSEMI

安森美半导体

TTL HD74/HD74S Series

文件：143.51 Kbytes 页数：4 Pages

HitachiHitachi Semiconductor

日立日立公司

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

文件：697.41 Kbytes 页数：17 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

文件：1.32368 Mbytes 页数：20 Pages

TI

德州仪器