Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

文件：53.28 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体

DUAL NEGATIVE-EDGE-TRIGGERED MASTER-SLAVE J-K FLIP-FLOPS WITH CLEAR AND COMPLEMENTARY OUTPUTS

文件：91.15 Kbytes 页数：3 Pages

NSC

国半

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

文件：121.86 Kbytes 页数：6 Pages

NSC

国半

Package：14-DIP（0.300"，7.62mm）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 14DIP

ONSEMI

安森美半导体