Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件：135 Kbytes 页数：6 Pages

NSC

国半

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件：135 Kbytes 页数：6 Pages

NSC

国半

Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t

文件：52.33 Kbytes 页数：5 Pages

Fairchild

仙童半导体

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件：135 Kbytes 页数：6 Pages

NSC

国半