Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t

文件：52.33 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件：135 Kbytes 页数：6 Pages

NSC

国半

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件：135 Kbytes 页数：6 Pages

NSC

国半

Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t

文件：52.33 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体

Dual J-K Positive-edge-triggered Flip-Flops(with Preset and Clear)

● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....)

文件：68.71 Kbytes 页数：6 Pages

HITACHIHitachi Semiconductor

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