Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

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FAIRCHILD

仙童半导体

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

ONSEMI

安森美半导体

DIP16

FSC

上传：深圳市乐创天科技有限公司

DIP16

FSC

上传：深圳市乐创天科技有限公司

DIP20

NSC

国半

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