Triple 3-Input NOR Gate

General Description This device contains three independent gates, each of which performs the logic NOR function. Features ■Switching specifications at 50 pF ■Switching specifications guaranteed over full temperature and VCCrange ■Advanced oxide-isolated, ion-implanted Schottky TTL

文件：46.43 Kbytes 页数：4 Pages

Fairchild

仙童半导体

Triple 3-Input NOR Gate

General Description\nThis device contains three independent gates, each of which performs the logic NOR function. Switching specifications at 50 pF\nSwitching specifications guaranteed over full temperature and VCC range\nAdvanced oxide-isolated, ion-implanted Schottky TTL process\nFunctionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart\nImproved AC performance over Schottky;

TI

德州仪器

Triple 3-Input NOR Gate

ONSEMI

安森美半导体

Octal D-Type Edge-Triggered Flip-Flop with Clear

General Description These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup requirements is transferred to the Q outputs on the positive-going edge of the clock pulse.

文件：183.6 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Octal D-Type Edge-Triggered Flip-Flop with Clear

General Description These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup requirements is transferred to the Q outputs on the positive-going edge of the clock pul

文件：76.76 Kbytes 页数：7 Pages

Fairchild

仙童半导体

Octal D-Type Edge-Triggered Flip-Flop with Clear

General Description These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup requirements is transferred to the Q outputs on the positive-going edge of the clock pul

文件：76.76 Kbytes 页数：7 Pages

Fairchild

仙童半导体

Octal D-Type Edge-Triggered Flip-Flop with Clear

General Description These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup requirements is transferred to the Q outputs on the positive-going edge of the clock pulse.

文件：183.6 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Octal D-Type Edge-Triggered Flip-Flop with Clear

General Description These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup requirements is transferred to the Q outputs on the positive-going edge of the clock pulse.

文件：183.6 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Octal D-Type Edge-Triggered Flip-Flop with Clear

General Description These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup requirements is transferred to the Q outputs on the positive-going edge of the clock pul

文件：76.76 Kbytes 页数：7 Pages

Fairchild

仙童半导体

Octal D-Type Edge-Triggered Flip-Flop with Clear

General Description These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup requirements is transferred to the Q outputs on the positive-going edge of the clock pulse.

文件：183.6 Kbytes 页数：9 Pages

ONSEMI

安森美半导体