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DFPIC166X数据手册Microchip中文资料规格书

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厂商型号

DFPIC166X

功能描述

FPGA IP Cores

制造商

Microchip Microchip Technology

中文名称

微芯科技 微芯科技股份有限公司

数据手册

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更新时间

2025-8-16 20:00:00

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DFPIC166X规格书详情

描述 Description

Description: DFPIC166X High Performance Configurable 8-bit RISC MicrocontrollerThe DFPIC166X is a low-cost, high performance, 8-bit, fully static soft IP Core, dedicated for operation with fast (typically on-chip) dual ported memory. The core has been designed with a special concern about low power consumption. DFPIC166X soft core is software-compatible with the industry standard PIC16C6X. It implements an enhanced Harvard architecture (i.e. separate instruction and data memories) with independent address and data buses. The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations to occur simultaneously. The advantage of this architecture is that instruction fetch and memory transfers can be overlapped by multi stage pipeline, so that the next instruction can be fetched from program memory while the current instruction is executed with data from the data memory. The DFPIC166X architecture is 2 times faster compared to standard architecture. The DFPIC166X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode make this IP perfect for applications where power consumption is critical. DFPIC166X is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.To obtain more information or to obtain this core, please contact Digital Core Design. Key Features: Software compatible with industry standard PIC16C6X Improved architecture 2 times faster compared to original implementation 35 – 14 bit wide instructions 512 bytes of internal Data Memory Optional RAM extension up to 32 kB Up to 64K bytes of Program Memory Configurable hardware stack Power saving SLEEP mode Fully synthesizable, static synchronous design with no internal tri-states DFPIC166X requires 3,134 Tiles in Actel's ProASIC3 Device, with -2 speed grade for 33 MHz operation DFPIC166X requires 3,023 Tiles in Actel's Fusion Device, with -2 speed grade for 34 MHz operation DFPIC166X requires 3,124 Tiles in Actel's IGLOO Device, with -2 speed grade for 20 MHz operation DocumentsDFPIC166XDatasheet For more information/ To register interest, please click here

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