DFPIC1655X中文资料FPGA IP Cores数据手册Microchip规格书

描述 Description

Description: DFPIC1655X High Performance Configurable 8-bit RISC Microcontroller The DFPIC1655X is a low-cost, high performance, 8-bit, fully static soft IP Core, dedicated for operation with fast memory (typically on-chip). The core has been designed with a special concern about low power con-sumption. The DFPIC1655X is software compatible with the industry standard PIC16C554 and PIC16C558. It employs a modified RISC architecture (2 times faster than original implementation). The DFPIC1655X have enhanced core features, configurable hardware stack, and multiple internal and external interrupt sources. The separate instruction and data buses allow a 14 bit wide instruction word with the separate 8 -bit wide data. The DFPIC1655X typically achieve a 2:1 code compression and a 8:1 speed improvement over other 8-bit microcontrollers in their class. The power-down mode SLEEP allow user to reduce power consumption. User can wake up the controller from SLEEP through several external and internal interrupt and reset. An integrated Watchdog Timer with it's own clock signal provides protection against software lock-up. The DFPIC1655X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode and small used area in programmable devices make this IP perfect for applications applications with space and power consumption limitations. DFPIC1655X is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.To obtain more information or to obtain this core, please contact Digital Core Design. Key Features: Software compatible with industry standard PIC16C55X Harvard architecture 2 times faster com-pared to original implementation 35 instructions 14 bit wide instruction word Up to 512 bytes of internal Data Memory Up to 64K bytes of Program Memory Configurable hardware stack Power saving SLEEP mode Fully synthesizable, static synchronous design with no internal tri-states Scan test ready DFPIC1655X requires 1,619 Tiles in Actel's ProASIC3 Device, with -2 speed grade for 36 MHz operation DFPIC1655X requires 1,519 Tiles in Actel's Fusion Device, with -2 speed grade for 38 MHz operation DFPIC1655X requires 1,538 Tiles in Actel's IGLOO Device, with -2 speed grade for 20 MHz operation DocumentsDFPIC1655XDatasheet For more information/ To register interest, please click here