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DAC1658Q1G0NAGA8中文资料瑞萨数据手册PDF规格书

DAC1658Q1G0NAGA8
厂商型号

DAC1658Q1G0NAGA8

功能描述

Quad 16-bit DAC: 10 Gbps JESD204B interface: x2, x4 and x8 interpolating

文件大小

10.06356 Mbytes

页面数量

165

生产厂商 Renesas Technology Corp
企业简称

RENESAS瑞萨

中文名称

瑞萨科技有限公司官网

原厂标识
RENESAS
数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-8-4 15:12:00

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DAC1658Q1G0NAGA8规格书详情

FEATURES AND BENEFITS

 Quad channel 16-bit resolution

 2 GSps maximum output update rate

 JEDEC JESD204B device subclass I compatible:

SYSREF based deterministic and repeatable interface

latency

 Multiple device synchronization enables multiple DAC

channels to be sample synchronous and phase coherent

to within one DAC clock period

 Up to 8 configurable JESD204B serial input lanes

running up to 10 Gbps with embedded termination and

programmable equalization gain (CTLE)

 SPI interface (3-wire or 4-wire mode) for control setting

and status monitoring

 Flexible SPI power supply (1.8 V or 1.2 V) ensuring

compatibility with on-board SPI bus

 Differential scalable output current from 10 mA to 30 mA

 Two embedded NCO with 40-bit programmable

frequency and 16-bit phase adjustment

 Embedded complex (IQ) digital modulator

 Very low noise bypass-able integrated Phase-Locked

Loop (PLL); no external capacitors

 1.2 V and 3.3 V power supplies (for DAC1653Q series,

the 3.3V supply voltage can be lowered to 2.8V for lower

power consumption)

 Flexible differential SYNC signals power supply (1.8 V or

1.2 V) ensuring compatibility with on-board devices

 Embedded Temperature Sensor

 Configurable IOs pins for monitoring, interrupt

 XBERT features (PRBS31, 23, 15, 7, JTSPAT, STLTP)

 SFDR = 87 dBc typical (band = Nyquist, fs = 1.50 Gsps;

interpolation 2; fout = 50 MHz)

 NSD = 164 dBm/Hz typical (fo = 20 MHz)

 IMD3 = 86 dBc typical (fs = 1.50 Gsps; interpolation 2;

fo1 = 150 MHz; fo2 = 151 MHz)

 Four carriers WCDMA ACLR = 75 dBc typical

(fs = 1.50 Gsps; fNCO = 350 MHz)

 RF enable/disable pin and RF automatic mute

 Clock divider by 2, 4, 6 and 8 available at the input of the

clock path

 Group delay compensation

 Embedded Power On Reset

 Power-down mode controls

 On-chip 0.7 V reference

 Industrial temperature range 40 C to +85 C

 Low (DAC1653Q) or high (DAC1658Q) common-mode

output voltage

 HLA 72 pins package (10 mm ´ 10 mm)

 Lane swapping and polarity swapping

 Signal Power Detector, IQ-Range detector, Level

detectors with Auto-Mute feature

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