DAC1653D2G0NLGA集成电路（IC）的数模转换器（DAC）规格书PDF中文资料

FEATURES AND BENEFITS

 Dual channel 16-bit resolution

 2.0 GSps maximum output update rate

 JEDEC JESD204B device subclass I compatible:

SYSREF based deterministic and repeatable interface

latency

 Multiple device synchronization enables multiple DAC

channels to be sample synchronous and phase coherent

to within one DAC clock period

 1, 2 or 4 configurable JESD204B serial input lanes

running up to 10 Gbps with embedded termination and

programmable equalization gain (CTLE)

 1 Gsps maximum baseband input data rate

 SPI interface (3-wire or 4-wire mode) for control setting

and status monitoring

 Differential scalable output current from 10 mA to 30 mA

 Embedded NCO with 40-bit programmable frequency

and 16-bit phase adjustment

 Embedded complex (IQ) digital modulator

 1.2 V and 3.3 V power supplies (for DAC1653D series,

the 3.3V supply voltage can be lowered to 2.7V for lower

power consumption)

 Flexible SPI power supply (1.8 V or 1.2 V) ensuring

compatibility with on-board SPI bus

 Flexible differential SYNC signals power supply (1.8 V or

1.2 V) ensuring compatibility with on-board devices

 Embedded Temperature Sensor

 Configurable IOs pins for monitoring, interrupt

 XBERT features (PRBS31, 23, 15, 7, JTSPAT, STLTP)

 SFDRRBW = 88 dBc typical (fs = 1.50 Gsps;

interpolation 2; bandwidth = 250 MHz; fout = 150 MHz)

 NSD = 167 dBc/Hz typical (fo = 70 MHz)

 IMD3 = 85 dBc typical (fs = 1.50 Gsps; interpolation 2;

fo1 = 152 MHz; fo2 = 155.1 MHz)

 Four carriers ACLR = 76 dB typical (fs = 1.50 Gsps;

fNCO = 350 MHz)

 RF enable/disable pin and RF automatic mute

 Clock divider by 2, 4, 6 and 8 available at the input of the

clock path

 Group delay compensation

 Analog offset control (10-bit auxiliary DACs)

 Power-down mode controls

 On-chip 0.7 V reference

 Industrial temperature range 40 C to +85 C

 Low (DAC1653D) or high (DAC1658D) common-mode

output voltage

 VFQFP-N 56 package (8 mm  8 mm)

 Embedded Power On Reset

 Lane swapping and polarity swapping

 Signal Power Detector, IQ-Range detector, Level

detectors with Auto-Mute feature