18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

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CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

文件：662.26 Kbytes 页数：29 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and CY7C1320JV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Features ■ 18-Mbit d

文件：616.03 Kbytes 页数：26 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and CY7C1320JV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Features ■ 18-Mbit d

文件：616.03 Kbytes 页数：26 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and CY7C1320JV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Features ■ 18-Mbit d

文件：616.03 Kbytes 页数：26 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and CY7C1320JV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Features ■ 18-Mbit d

文件：616.03 Kbytes 页数：26 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and CY7C1320JV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Features ■ 18-Mbit d

文件：616.03 Kbytes 页数：26 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR II SRAM Two-Word Burst Architecture

Functional Description The CY7C1316KV18, CY7C1916KV18, CY7C1318KV18, and CY7C1320KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Features ■ 18-Mbit density

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CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata

RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for QDRI/DDRI/QDRII/DDRII. Details include trigger conditions, possible workarounds and silicon revision applicability. This document should be used to compare to th

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CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata

RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for QDRI/DDRI/QDRII/DDRII. Details include trigger conditions, possible workarounds and silicon revision applicability. This document should be used to compare to th

文件：243.48 Kbytes 页数：8 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司