CY7C1362A中文资料赛普拉斯数据手册PDF规格书

Functional Description

The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs integrate 262,144 ×36 and 524,288×18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2and CE3), burst control inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and BWE), and global Write (GW). However, the CE3chip enable input is only available for the TA package version.

Features

• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns

• Fast clock speed: 225, 200, 166, and 150 MHz

• Fast OEaccess times: 2.5 ns, 3.0 ns, and 3.5 ns

• Optimal for depth expansion (one cycle chip deselect to eliminate bus contention)

• 3.3V –5 and +10 power supply

• 3.3V or 2.5V I/O supply

• 5V-tolerant inputs except I/Os

• Clamp diodes to VSSat all inputs and outputs

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Multiple chip enables for depth expansion: three chip enables for A package version and two chip enables for BG and AJ package versions

• Address pipeline capability

• Address, data, and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst sequence)

• Automatic power-down feature available using ZZ mode or CE deselect

• JTAG boundary scan for BG and AJ package version

• Low-profile 119-bump, 14-mm × 22-mm PBGA (Ball Grid Array) and 100-pin TQFP packages