4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture

Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required

文件：539.56 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture

Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required

文件：539.56 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture

Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required

文件：539.56 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture

Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required

文件：539.56 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司