CY7C1340A中文资料赛普拉斯数据手册PDF规格书

Functional Description

The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors.

The CY7C1340A/GVT71128C32 SRAM integrates 131,072 × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

特性 Features

• Fast access times: 5 and 7 ns

• Fast clock speed: 100 and 66 MHz

• Provides high-performance 3-1-1-1 access rate

• Fast OE access times: 5 and 7 ns

• Optimal for performance (two-cycle chip deselect, depth expansion without wait state)

• Single +3.3V –5 and +10power supply

• Supports +2.5V I/O

• 5V tolerant inputs except I/Os

• Clamp diodes to VSSQ at all outputs

• Common data inputs and outputs

• Byte Write Enable and Global Write control

• Three chip enables for depth expansion and address pipeline

• Address, control, input, and output pipeline registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst sequence)

• Automatic power-down for portable applications

• High-density, high-speed packages

• Low-capacitive bus loading

• High 30-pF output drive capability at rated access time