2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

文件：575.53 Kbytes 页数：13 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

文件：575.53 Kbytes 页数：13 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

文件：575.53 Kbytes 页数：13 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

文件：575.53 Kbytes 页数：13 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

文件：575.53 Kbytes 页数：13 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2-Mbit (64K x 32) Pipelined SRAM with NoBL™ Architecture

Infineon

英飞凌

Package：100-LQFP；包装：卷带（TR） 类别：集成电路（IC） 存储器 描述：IC SRAM 2MBIT PARALLEL 100TQFP

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司