18-Mbit QDR II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat

文件：689.64 Kbytes 页数：27 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat

文件：689.64 Kbytes 页数：27 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat

文件：689.64 Kbytes 页数：27 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat

文件：689.64 Kbytes 页数：27 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司