64K x 18 Synchronous Cache RAM

Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the add

文件：282.21 Kbytes 页数：13 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

64K x 18 Synchronous Cache RAM

Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the add

文件：282.21 Kbytes 页数：13 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

64K x 18 Synchronous Cache RAM

Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the add

文件：282.21 Kbytes 页数：13 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

64K x 18 Synchronous Cache RAM

Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the add

文件：282.21 Kbytes 页数：13 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

64K x 18 Synchronous Cache RAM

Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the add

文件：282.21 Kbytes 页数：13 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

64K x 18 Synchronous Cache RAM

Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the add

文件：282.21 Kbytes 页数：13 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

64K x 18 Synchronous Cache RAM

Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the add

文件：282.21 Kbytes 页数：13 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

6-Mbit (256K X 24) Static RAM

文件：300.51 Kbytes 页数：8 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

6-Mbit (256K X 24) Static RAM

文件：443.05 Kbytes 页数：9 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

6-Mbit (256K X 24) Static RAM

文件：443.05 Kbytes 页数：9 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司