CY7C1032-8JC中文资料赛普拉斯数据手册PDF规格书

Functional Description

The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

特性 Features

• Supports 66-MHz Pentium® microprocessor cache systems with zero wait states

• 64K by 18 common I/O

• Fast clock-to-output times

— 8.5 ns

• Two-bit wraparound counter supporting Pentium microprocessor and 486 burst sequence (7C1031)

• Two-bit wraparound counter supporting linear burst sequence (7C1032)

• Separate processor and controller address strobes

• Synchronous self-timed write

• Direct interface with the processor and external cache controller

• Asynchronous output enable

• I/Os capable of 3.3V operation

• JEDEC-standard pinout

• 52-pin PLCC packaging