CY74FCT823T中文资料具有三态输出的 9 位总线接口触发器数据手册TI规格书

描述 Description

This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a 9-bit-wide buffered register with clock-enable (EN\\) and clear (CLR\\) inputs that are ideal for parity bus interfacing in high-performance microprogrammed systems. It is ideal for use as an output port requiring high IOL/IOH. This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特性 Features

• Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29823
• Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
• Matched Rise and Fall Times
• ESD Protection Exceeds JESD 22
• 200-V Machine Model (A115-A)
• 64-mA Output Sink Current 32-mA Output Source Current
• Buffered Common Clock-Enable (EN\\) and Asynchronous-Clear (CLR\\) Inputs
• 3-State Outputs